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24AA1026/24LC1026/24FC1026
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1 .
TABLE 2-1:
PIN FUNCTION TABLE
Name
NC
A1
A2
V SS
SDA
SCL
WP
V CC
PDIP
1
2
3
4
5
6
7
8
SOIJ
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
Function
Not Connected
User Configurable Chip Select
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1026)
+2.5 to 5.5V (24LC1026)
+1.8 to 5.5V (24FC1026)
2.1
A1, A2 Chip Address Inputs
The A1 and A2 inputs are used by the 24XX1026 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A1 and A2 are
hard-wired to logic ‘ 0 ’ or logic ‘ 1 ’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘ 0 ’ or logic ‘ 1 ’ before normal
device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V CC (typical 10 k ? for 100 kHz, 2 k ?? for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4
Write-Protect (WP)
This pin must be connected to either V SS or V CC . If tied
to V SS , write operations are enabled. If tied to V CC ,
write operations are inhibited, but read operations are
not affected.
? 2011-2012 Microchip Technology Inc.
DS22270C-page 5
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